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再以整体营收来看，可发现随着时间季度推进，稳懋基地台设备产值更有逐季提升趋势，甚至2019年*二季已达到高点4千1百万美元，推升该季营收表现，因此虽受中美贸易战影响，但现阶段5G通讯设备发展与布局仍持续进行中，对于稳懋GaN元件于基地台设备的使用与建置上，其营收方面将逐渐摆脱中美摩擦阴霾。

Microsemi公司的MSCMDD/REF1是双路SiC MOSFET驱动器参考设计,是开源解决方案,提供了用户友好的设计指南,使得用户采用MicrosemiSiC MOSFET能更快地走向市场.参考设计还支持过度到下代SiC MOSFET,新的参考设计为用户提供了高度绝缘的SiC MOSFET双栅较驱动器开关,用作评估各种拓扑中SiC MOSFET的方法.这包括有同步死区时间保护的半桥开关闭优化模式,以及没有保护的异步信号传输.它还配置成提供共流驱动以了解无阻尼感应开关(UIS)或双脉冲测试.参考设计仅需要24V电源输入,两个栅较驱动的隔离大于2000V,每边栅较驱动能力8W,栅较驱动电压–5 V/20 V,峰值输出电流高达±30 A,高达400kHz开关频率,单端或RS485/RS422差分输入栅较控制,±100 kV/μs功能,故障信令,可配置开关死区时间,非常低的时序抖动.主要用在航空**(激励,空调,电源分配),汽车电子(混合/电动汽车动力总成,电动汽车电池充电器,DC/DC转换器和能量恢复),*(电源,大功率马达驱动),工业(光伏逆变器,马达驱动,焊接机,UPS,开关电源,电感加热,石油钻井)以及医疗(MRI,X射线电源).本文介绍了SiCMSCMDD/REF1参考设计主要特性,框图和半桥框图,电路图和材料清单.
The dual SiC MOSFET driver reference design is an open-source solutionthat provides user-friendly design guides, enabling faster time-to-marketfor customers using MicrosemiSiC MOSFETs. The reference design alsosupports the transition to Microsemi’s next-generation SiC MOSFETs.
The new reference design provides customers with a highly isolated SiCMOSFET dual-gate driver switch as a means of evaluating SiC MOSFETsin a number of topologies. This includes modes optimized for half-bridgeswitching with synchronous dead-time protection and asynchronous** transfer with no protection. It can also be configured to provideconcurrent drive to study unclamped inductive switching (UIS) or doublepulse testing. The board supports the modification of gate resistor values toaccommodate most Microsemidiscretes and modules.
The dual SiC MOSFET driver reference design is ideal for a wide rangeof end markets and applications, including aerospace (actuation, airconditioning, and power distribution), automotive (hybrid/electric vehiclepowertrains), electric vehicle battery chargers, DC-to-DC converters, andenergy recovery), defense (power supply and high-power motor drive),industrial (photovoltaic inverters, motor drives), welding, uninterruptiblepower supply, switched-mode power supply, induction heating, and oildrilling), and medical (MRI and X-ray power supply).
SiCMSCMDD/REF1参考设计主要特性:
• Switch configurable as either a high/low sidedriver with half bridges or independent drive
• Requires only a 24 V power input
• Galvanic isolation of more than 2000 V on bothgate drivers
• Capable of 8 W of gate drive power per side
• Peak output current of up to ±30 A
• Up to 400 kHz maximum switching frequency
• Single-ended or RS485/RS422 differential inputgate control
• Desaturation shoot-through (short-circuit)protection
• ±100 kV/μs capability
• Fault **ing
• SiC compatible under voltage lockoutprotection
• Gate drive voltage is –5 V/20 V and adjustablefor lower voltages
• Switch-configurable dead time
• Option of disabling shoot-through protection fordual switch UIS/RUIS testing
• Very low timing skew

ADI公司的ADAU1787是集成了两个数字信号处理器(DSP)的具有四个输入和两个输出的编译码器(CODEC).ADAU1787具有可编程的FastDSP音频处理引擎,高达768kHz取样速率,双二阶滤波器,限制器,音量控制和混合; ADAU1787还集成了SigmaDSP音频处理核,高达50MIPS性能,低延迟24位ADC和DAC.主要特性还具有96dB信噪比(SNR)(信号通过PGA和ADC与A加权滤波器)以及105dB组合SNR(信号通过DAC和耳机与A加权滤波器),串口fSYNC频率从8kHz到192kHz,模拟进到模拟出的群时延为5 μs (fS = 768 kHz),4个单端模拟输入,可配置麦克风或线输入,8个数字麦克风输入,2个模拟差分音频输出可配置成线输出或耳机驱动器,锁相环(PLL)支持30kHz到27MHz任何输入时钟速率,主要用在降噪手持机和耳机,蓝牙ANC手持机和耳机,个人导航设备(PND),数码相机和摄像机,音乐乐器效果处理器,多媒体扬声器系统和智能手机.本文介绍了ADAU1787主要特性,框图和系统框图以及评估板EVAL-ADAU1787Z主要特性,电路图,材料清单和PCB设计图.
The ADAU1787 is a codec with four inputs and two outputs that incorporates two digital ** processors (DSPs). The path from the og input to the DSP core to the og output is optimized for low latency and is ideal for noise cancelling headsets. With the addition of just a few passive components, the ADAU1787 provides a complete headset solution.
Note that throughout this data sheet, multifunction pins, such as BCLK_0/MP1, are referred to either by the entire pin name or by a single function of the pin, for example, BCLK_0, when only that function is relevant.
ADAU1787主要特性:
Programmable FastDSP audio processing engine
Up to 768 kHz sample rate
Biquad filters, limiters, volume controls, mixing
28-bit SigmaDSP audio processing core
Visually programmable using SigmaStudio
Up to 50 MIPS performance
Low latency, 24-bit ADCs and DACs
96 dB SNR (** through PGA and ADC with A-weighted filter)
105 dB combined SNR (** through DAC and headphone with A-weighted filter) Serial port fSYNC frequency from 8 kHz to 192 kHz
5 μs group delay (fS = 768 kHz) og in to og out with FastDSP bypass
4 single-ended og inputs, configurable as microphone or line inputs
8 digital microphone inputs
2 og differential audio outputs, configurable as either line output or headphone driver
PLL supporting any input clock rate from 30 kHz to 27 MHz
Full-duplex, 4-channel ASRCs
2,16-channel serial audio ports supporting I2S, left justified,or up to TDM16
8 interpolators and 8 decimators with flexible routing
Power supplies
og AVDD at 1.8 V typical
Digital I/O IOVDD at 1.1 V to 1.98 V
Digital DVDD at 0.9 V typical
Low power (11.027 mW for typical stereo noise cancelling solution)
I2C and SPI control interfaces, self boot from I2C EEPROM
Flexible GPIO
42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP